A typical example of the operational amplifier circuit is illustrated in FIG. 1 of the drawings and largely comprises a differential amplifier input stage 1, an output stage 2, a phase compensating circuit 3 and a biasing circuit 4. The differential amplifier input stage 1 is coupled between two voltage sources Vdd and Vss producing respective voltage levels different in value and has a pair of input transistors 5 and 6 the gate electrodes of which are coupled to an inverting input node 7 and a non-inverting input node 8, respectively. The inverting input node 7 is supplied with a ground voltage level and the non-inverting input node 8 is applied with an input voltage signal. The differential amplifier input stage 1 further has two load transistors 9 and 10 coupled in parallel between the voltage source Vdd and the input transistors 5 and 6, and a current source transistor 11 coupled between the input transistors 5 and 6 and the voltage source Vss for supplying a a constant current to the input transistors 5 and 6. The transistors 5, 6 and 11 are of the n-channel type but the transistors 9 and 10 are formed by p-channel type field effect transistors, respectively. A node shared by the transistors 6 and 10 serves as an output node of the differential amplifier input stage 1. The differential amplifier input stage 1 thus arranged is responsive to a difference in voltage level between the inverting input node 7 and the non-inverting input node 8, and the difference in voltage level is increased in value by the function of the input transistors 5 and 6 in association with the common transistor 11, thereby producing an inverting voltage signal at the node 12 with respect to the input voltage signal applied to the input node 8.
The output stage 2 has two transistors 13 of the p-channel type and 14 of the n-channel type coupled in series between the two voltage sources Vdd and Vss, and an output node 15 thereof is provided between the two transistors 13 and 14. The transistor 13 has a gate electrode tied to the node 12 of the differential amplifier input stage 1, so that the transistor 13 serves as a current driving transistor which produces a non-inverting output voltage signal at the output node 15 which varies in a symmetrical manner with respect to the inverting voltage signal at the node 12 in association with the transistor 14 of a constant current source.
The phase compensating circuit 3 is provided with a series combination of a capacitor 16 and a resistor 17 coupled between the node 12 and the output node 15, and the series combination is operative to compensate an irregular distortion in the output voltage at the node 12 due to, for example, a noise riding on the current supplied from the voltage source Vdd. The biasing circuit 4 has a series combination of a constant current source 18 and an n-channel type transistor 19 coupled between the voltage sources Vdd and Vss, and the transistor 19 has a gate electrode tied to not only the constant current source 18 but also the gate electrodes of the transistors 11 and 14 to form in combination a current mirror circuit for causing the transistors to serve as the constant current sources, respectively.
The operational amplifier circuit thus arranged produces the non-inverting output voltage signal at the output node 15 and further compensates the irregular distortion due to the fluctuation of the voltage level supplied from the constant voltage source. However, a problem is encountered in the prior-art operational amplifier circuit in undesirable distortion of the non-inverting output voltage signal in a high frequency operation due to fluctuation of the voltage level supplied from the voltage source.
Another prior-art operational amplifier circuit is disclosed by DeWitt G. ONG in pages 233 to 235 of "Modern MOS Technology: Processes, Devices, and Design" published in 1984 by McGraw-Hill Book Company. The operational amplifier circuit disclosed by DeWitt G. ONG is implemented by CMOS inverters and comprises a differential amplifier input stage and an output stage but no phase compensating circuit is incorporated.